1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a write training operation of a semiconductor device.
2. Description of the Related Art
In a system including a plurality of semiconductor devices, a semiconductor device corresponding to a transmitter generates and outputs a signal on the basis of a system clock and the signal, and a semiconductor device corresponding to a receiver performs a predetermined operation based on the system dock and the signal. If a semiconductor device corresponding to a transmitter is a memory controller and a semiconductor device corresponding to a receiver is a semiconductor memory device, for example a DDR SDRAM, the system clock serves as an operation clock, the signal as a data signal, and the predetermined operation as an operation of receiving and storing the data signal.
If the transmitter sends the signal to the receiver by using a source synchronization method, the signal and the system dock are transmitted while synchronizing a specific edge of the signal with a specific edge of the system clock. Here, assuming that the channel of the transmitted signal has the same length as the channel of the transmitted system clock, the specific edge of the signal is synchronized with the specific edge of the system clock and both the signal and the system clock are applied to the receiver.
Meanwhile, in order to determine whether a logic value of the signal transmitted from the transmitter to the receiver is ‘1’ or ‘0’, the specific edge of the system clock needs to be placed at the center of the signal, since certain setup and hold time is necessary for recognizing the signal.
That is, the signal is transmitted from the transmitter to the receiver while synchronizing the specific edge of the signal with the specific edge of the system clock. The phase of the system clock applied to the receiver needs to be shifted by 90 degrees because the specific edge of the system clock needs to be placed at the center of the signal at the receiver.
Furthermore, if the length of a channel through which the system clock is transmitted is different from the length of a channel through which the signal is transmitted, it may be necessary to additionally compensate for a difference in the delay amount due to a difference in the length of the channels. That is, when the transmitter synchronizes the specific edge of the signal with the specific edge of the system dock and sends the signal and the system block, the system clock and the signal are out of synchronization at the receiver due to a difference in the transmission delay amount. It may be necessary to compensate for a difference in the transmission delay amount.
Accordingly, a process of the receiver for adjusting a phase relationship between the signal and the system clock, which are applied to the receiver while having specific edges synchronized with each other after the receiver is initially powered up is performed in a specific initial period, so that the specific edge of the system clock is placed at the center of the signal. Such process is called write training operation.
In order to precisely recognize the specific edge of the system clock at the center of the signal in the write training operation, it may be more advantageous for a logic value of the signal, transmitted from the transmitter to the receiver, to have a specific pattern rather than a random pattern in the write training operation. For example, when the signal having a training pattern ‘1 0 0 0’ is transmitted from the transmitter to the receiver, a phase relationship between the signal and the system clock may be easily trained because a case where a first logic value of the signal recognized in the receiver is ‘1’ and the remaining logic values thereof are ‘0’ has only to be searched for. That is, the specific edge of the system clock may be placed at the center of the signal by shifting a phase of the system clock until a logic value of the signal is recognized as being ‘1 0 0 0’ although the signal applied early in the write training operation is not recognized as being a logic value ‘1 0 0 0’.
However, a time taken to recognize a logic value of the signal as being ‘1 0 0 0’ may differ depending on an initial phase relationship between the signal and the system clock at the receiver. Furthermore, in order to precisely place the specific edge of the system clock at the center of the signal, both rising and falling edges of a pulse corresponding to ‘1’ in the training pattern ‘1 0 0 0’ must be detected.
In this case, the time taken to execute the write training operation may increase.